Among the continuing scaling of CMOS technology toward deep submicron range, the supply voltage is scaled to 1.5V to 1.8V range at current 0.18um to 0.15um manufacturing processes. Phase-Locked Loop (PLL) is one of the most important blocks for almost all high-performance digital chips such as CPUs, DSPs, communication transmitter/receivers, etc. However, as an analog circuit, PLL's control voltage range becomes more limited as the supply voltage becomes lower. Thus, a need exists for a CMOS PLL design for low-supply voltage and high-speed clock generation.